• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a configuration for the measurement of internal voltages in a DUT (2), in which a comparator (3) is provided in each DUT (2) and compares the internal voltage (Vint) to be measured with an externally supplied reference voltage (Vref).
    公开号:US20010005143A1
    申请号:US09/740,633
    申请日:2000-12-18
    公开日:2001-06-28
    发明作者:Peter Beer；Carsten Ohlhoff
    申请人:Infineon Technologies AG；
    IPC主号:G01R31-2884
    专利说明:
    [0001] Field of the Invention [0001]
    [0002] The present invention relates to a configuration for the measurement of internal voltages in an integrated semiconductor apparatus. [0002]
    [0003] Various internal voltages, which may have values of, for example, 2.3 V, 3.5 V, 0.9 V etc., are required in integrated semiconductor apparatuses, such as memory chips etc. These internal voltages in an integrated semiconductor apparatus must be checked before these apparatuses are delivered to ensure that the integrated semiconductor apparatus operates reliably. In the past, testers have been used for this purpose, each of which contains a DC voltage unit (“DC Unit”) that applies a known DC voltage (reference voltage) to the semiconductor apparatus, that is to say a memory chip for example. Such a tester would at the same time measure the internal voltage to be checked. In the above example, an internal voltage of 2.3 V, 3.5 V or 0.9 V would be measured on a pad (contact cushion), that is suitable for this purpose, of the semiconductor apparatus. [0003]
    [0004] The semiconductor apparatuses to be tested, also referred to as DUTs (“Device Under Test”) now require as many DC voltage units as DUTs in order to perform parallel measurements; each DUT is allocated its own DC voltage unit for the parallel measurement. [0004]
    [0005] If the goal is to test the internal voltages in a large number of semiconductor apparatuses, such as SDRAMs, then an equally large number of DC voltage units are required in the tester in order to perform parallel measurements. Such parallel measurement is a precondition for a short measurement time, and this makes the tester extremely complex. [0005] SUMMARY OF THE INVENTION
    [0006] It is accordingly an object of the invention to provide a configuration and a method for the measurement of internal voltages in an integrated semiconductor apparatus which overcomes the above-mentioned disadvantageous of the prior art configurations and methods of this general type, and that enables a large number of such integrated semiconductor apparatuses to be measured in parallel, with a low level of complexity. [0006]
    [0007] With the foregoing and other objects in view there is provided, in accordance with the invention, a configuration for measuring an internal voltage in an integrated semiconductor apparatus. The configuration includes a tester supplying a reference voltage, and a semiconductor apparatus having an internal voltage to be measured and a comparator with a first input, a second input, and an output. The first input of the comparator has the internal voltage to be measured applied thereto. The second input of the comparator has the reference voltage applied thereto, and the output of the comparator is connected to the external tester. The tester is disposed external from the semiconductor apparatus and is configured to determine whether the internal voltage matches or does not match the reference voltage. [0007]
    [0008] The reference voltage can be supplied to the comparator in discrete voltage steps, or as a ramp signal. [0008]
    [0009] The invention thus departs completely from the approach used in the previous prior art; the comparator which compares the internal voltage (Vint) to be measured with a reference voltage (Vref) is moved to the semiconductor apparatus, that is to say to the DUT so that a large number of semiconductor apparatuses or DUTs can be measured in parallel directly, by comparing the one externally supplied reference voltage with the corresponding internal voltage in the respective semiconductor apparatuses. The additional complexity for the comparator is relatively low, and requires only a small surface area on the integrated semiconductor apparatus. [0009]
    [0010] The reference voltage is applied via a pad or contact cushion, and this reference voltage together with the internal voltage to be measured is passed to the inputs of the comparator that is provided in the semiconductor apparatus. The output from this comparator is passed to the outside. This means that the reference voltage is supplied from an external tester, which also records the output signal from the comparator. The output signal can in this case be output directly to the external tester, via a suitable pad. Alternatively, a suitable monitoring signal (for example “high” = Vint is greater than Vref; “low” = Vint is less than Vref) could also be output via one of the existing input/output channels of the semiconductor apparatus. [0010]
    [0011] If, for example, the output signal from the comparator is at a high level, then this may mean that the internal voltage is less than the reference voltage. On the other hand, if the output signal from the comparator is at a low level, then this means that the internal voltage is higher than the reference voltage. [0011]
    [0012] In order now to measure the internal voltage, one option is to apply the reference voltage in discrete voltage steps, with an external check being carried out with the tester after each voltage step to determine whether the values of the internal voltage and of the reference voltage have already crossed. If such a crossover occurs, then this means that the internal voltage matches the external reference voltage with the accuracy provided by the step widths. [0012]
    [0013] Another option is to apply the reference voltage to the comparator as a ramp signal. In this case, the internal voltage in the semiconductor apparatus corresponds to the reference voltage at the time at which the output from the comparator signals that the internal voltage and the reference voltage have crossed over. [0013]
    [0014] The comparator is preferably a differential amplifier. However, it is, of course possible, to choose any circuit for the comparator which is able to compare the external reference voltage with the internal voltage to be measured. [0014]
    [0015] With the foregoing and other objects in view there is also provided, in accordance with the invention, a method for testing a plurality of integrated semiconductor components, which comprises steps of: [0015]
    [0016] providing each of a plurality of integrated semiconductor components with an input for receiving a reference voltage; [0016]
    [0017] connecting the input of each of the plurality of integrated semiconductor components in parallel and supplying the reference voltage to each input; [0017]
    [0018] for each of the plurality of integrated semiconductor components, measuring a magnitude of a respective internal voltage by comparing the reference voltage with the respective internal voltage; and [0018]
    [0019] identifying operability of a respective one of the plurality of integrated semiconductor components as a function of the measured magnitude of the respective internal voltage. [0019]
    [0020] In accordance with an added mode of the invention, a voltage generator which produces the internal voltage is corrected as a function of the measured internal voltage. [0020]
    [0021] Other features which are considered as characteristic for the invention are set forth in the appended claims. [0021]
    [0022] Although the invention is illustrated and described herein as embodied in a configuration for measurement of internal voltages in an integrated semiconductor apparatus, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. [0022]
    [0023] The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. [0023] BRIEF DESCRIPTION OF THE DRAWINGS
    [0024] FIG. 1 shows a block diagram of a configuration for measuring internal voltages. [0024] DESCRIPTION OF THE PREFERRED EMBODIMENTS
    [0025] Referring now to the sole drawing figure, FIG. 1, in detail, there is shown an external tester [0025] 1 and a semiconductor apparatus (DUT) 2. One output of the external tester 1 supplies a reference voltage Vref to an input or pad of the semiconductor apparatus (DUT) 2, in which a differential amplifier 3 is integrated as a comparator. An internal voltage Vint to be measured is applied to one input of this differential amplifier 3, while the reference voltage Vref is supplied to the other input of the differential amplifier 3. The output signal from the differential amplifier 3 is supplied to the external tester 1 via an appropriate pad. The internal voltage Vint is obtained from circuitry 5 disposed in the semiconductor apparatus.
    [0026] The reference voltage Vref may be applied to the differential amplifier [0026] 3 either as a stepped signal in discrete voltage steps, or as a continuous ramp signal. As soon as the reference voltage Vref crosses the internal voltage Vint, the output signal from the differential amplifier 3 switches from “high” to “low”, or vice versa. This makes it possible to accurately define a match between the reference voltage and the internal voltage, that is to say the magnitude of the internal voltage.
    [0027] The reference voltage may, of course, be supplied in parallel to a large number of semiconductor apparatuses (DUTs), and their output signals can be recorded by the tester [0027] 1. This means that a large number of semiconductor apparatuses can be tested in parallel, directly, using only one reference voltage.
    [0028] Furthermore, the reference voltage supplied by the tester [0028] 1 may also be variable, so that the tester 1 can emit, for example, reference voltages of 2.3 V, 3.5 V and 0.9 V.
    [0029] If a reference voltage is applied in voltage steps, then the measurement accuracy becomes greater. Of course, the smaller the individual steps, the greater the accuracy. Better accuracy than this can be achieved by using a ramp signal as the reference voltage since, in that case, the crossover between the reference voltage and the internal voltage can be measured accurately. [0029]
    [0030] The configuration according to the invention allows a large number of integrated semiconductor chips to be tested in parallel. The semiconductor chips for testing are normally configured on a test board. The tester uses a single voltage generator to produce a single reference voltage with a ramp profile, which is supplied to all the chips which are to be tested in parallel. Since only a limited number of voltage generators are available on the tester, resources are saved there. Each of the chips to be tested emits a digital pulse via the internal-chip comparator [0030] 3. To receive these digital pulses, the tester has a large number of input channels. The invention thus makes it possible to test a large number of chips in parallel without any problems.
    [0031] As an example, let the nominal value of the voltage to be tested be 2.3 V. Those chips are found to be good whose internal voltage is within a tolerance band around 2.3 V, for example from 2.2 V to 2.4 V. Chips which supply internal voltages Vint outside this tolerance band are rejected as being unusable. If necessary, voltage generators inside the chip can be readjusted, that is to say trimmed, depending on the measurement result. The trimming is carried out by connecting or disconnecting reference elements within the voltage generators with fuses. A generator which produces the internal voltage Vint is in this way corrected, that is to say trimmed. [0031]
    权利要求:
    Claims (9)
    [1" id="US-20010005143-A1-CLM-00001] 1. A configuration for measuring an internal voltage in an integrated semiconductor apparatus, which comprises:
    a tester supplying a reference voltage;
    a semiconductor apparatus having an internal voltage to be measured and a comparator with a first input, a second input, and an output, said first input of said comparator having the internal voltage to be measured applied thereto, said second input of said comparator having said reference voltage applied thereto, said output of said comparator connected to said external tester;
    said tester disposed external from said semiconductor apparatus and configured to determine whether the internal voltage matches or does not match the reference voltage.
    [2" id="US-20010005143-A1-CLM-00002] 2. The configuration according to
    claim 1 , wherein said tester supplies the reference voltage to said comparator in discrete voltage steps.
    [3" id="US-20010005143-A1-CLM-00003] 3. The configuration according to
    claim 1 , wherein said tester supplies the reference voltage to said comparator as a ramp signal.
    [4" id="US-20010005143-A1-CLM-00004] 4. The configuration according to
    claim 1 , wherein the reference voltage is supplied to the semiconductor apparatus via a pad.
    [5" id="US-20010005143-A1-CLM-00005] 5. The configuration according to
    claim 1 , wherein said output of said comparator supplies a signal that makes a transition when the reference voltage crosses the internal voltage, said transition selected from the group consisting of transition from a high level to a low level and a transition from a low level to a high level.
    [6" id="US-20010005143-A1-CLM-00006] 6. The configuration according to
    claim 1 , wherein said comparator is a differential amplifier.
    [7" id="US-20010005143-A1-CLM-00007] 7. The configuration according to
    claim 1 , comprising a plurality of semiconductor apparatuses connected in parallel with said tester.
    [8" id="US-20010005143-A1-CLM-00008] 8. A method for testing a plurality of integrated semiconductor components, which comprises:
    providing each of a plurality of integrated semiconductor components with an input for receiving a reference voltage;
    connecting the input of each of the plurality of integrated semiconductor components in parallel and supplying the reference voltage to each input;
    for each of the plurality of integrated semiconductor components, measuring a magnitude of a respective internal voltage by comparing the reference voltage with the respective internal voltage; and
    identifying operability of a respective one of the plurality of integrated semiconductor components as a function of the measured magnitude of the respective internal voltage.
    [9" id="US-20010005143-A1-CLM-00009] 9. The method according to
    claim 8 , which comprises correcting a voltage generator which produces the internal voltage as a function of the measured internal voltage.
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    法律状态:
    2003-09-22| AS| Assignment|Owner name: INFENEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BEER, PETER;OHLHOFF, CARSTEN;REEL/FRAME:014504/0676 Effective date: 20010109 |
    2003-11-13| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2004-08-24| CC| Certificate of correction|
    2007-05-29| FPAY| Fee payment|Year of fee payment: 4 |
    2010-01-13| AS| Assignment|Owner name: QIMONDA AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:023773/0001 Effective date: 20060425 Owner name: QIMONDA AG,GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:023773/0001 Effective date: 20060425 |
    2011-05-27| FPAY| Fee payment|Year of fee payment: 8 |
    2015-05-08| AS| Assignment|Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA AG;REEL/FRAME:035623/0001 Effective date: 20141009 |
    2015-05-28| FPAY| Fee payment|Year of fee payment: 12 |
    2015-08-19| AS| Assignment|Owner name: POLARIS INNOVATIONS LIMITED, IRELAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:036396/0646 Effective date: 20150708 |
    优先权:
    申请号 | 申请日 | 专利标题
    DE19961107||1999-12-17||
    DE19961107||1999-12-17||
    DE19961107.6||1999-12-17||
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